Impedance trimming circuit

ABSTRACT

A common bias section is composed of a first series circuit having an internal resistor and an external resistor connected in series and an operational amplifier having a first input terminal connected to a reference voltage, a second input terminal connected to a Vr 1  node, and an output terminal connected to the series circuit. An impedance trimming section is composed of a series circuit having an internal resistor and an impedance dummy resistor connected in series, a comparator CMP having a first input terminal connected to the Vr 1  node and a second input terminal connected to a Vto 1  node, a code control circuit which uses a clock signal to latch an output signal from the comparator to generate a plurality of switching codes, and a switching circuit which switch a resistance value of the impedance dummy resistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This is a Continuation-in-Part application of U.S. patentapplication Ser. No. 10/608,364, filed Jun. 26, 2003, the entirecontents of which are incorporated herein by reference.

[0002] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Applications No. 2003-113191, filed Apr.17, 2003; and No. 2003-307766, filed Aug. 29, 2003, the entire contentsof both of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] The present invention relates to an LSI containing an impedancetrimming circuit to execute impedance matching on output impedance,input impedance, terminal resistance, or the like to suppress reflectionof signals, thus allowing high-speed serial signals of high quality tobe transferred, and in particular, to a trimming circuit for accurateand automatic adjustment.

[0005] 2. Description of the Related Art

[0006] For a high-speed interface such as a USB2.0 (480 Mbps) or an LUDS(several Gbps), it has hitherto been essential to match input impedance,drive impedance, pull-up/pull-down resistance, or the like with acorresponding standard value (for example, ±10%) in order to suppressreflection of the waveform of a transferred signal, thus allowing ahigh-speed signal of high quality to be transmitted.

[0007] However, resistance elements manufactured using an LSImanufacturing process vary markedly (for example, ±20%). Further, the onresistance of an output transistor depends significantly on atemperature, a power voltage, or a threshold (for example, worstbest=double/half). Accordingly, a certain adjustment circuit isrequired.

[0008] A first example of the prior art is Non-patent Document 1(ESSCIRC2001 “A New Impedance Control Circuit for USB2.0 Transceiver”Koo K. -H. SAMSUNG Electronics(http://www.esscirc.org/esscirc20001/C01_Presentations/5.pdf)).

[0009] In Non-patent Document 1, as shown in FIGS. 1 and 2, anoperational amplifier adjusts a voltage drop at an external resistorRext to an internal reference voltage Vref. An output signal from theoperational amplifier is supplied to gates of two P channel MOStransistors. An output signal from an output buffer appears as apositive and negative differential outputs at a Data+terminal and aData−terminal, respectively, on the basis of voltage drops at internalresistors. This circuit has an auxiliary circuit for adjustment inaddition to a circuit for data transfer. The auxiliary circuit finds, ina controlled manner, a code that adjusts the potential at a VA terminalto a value Vref.

[0010] In this case, output impedance is based on the internal resistorand MOS resistor. However, in this conventional example, this value isadjusted to 45Ω±5Ω. Specifically, a comparator and a control circuit areused to adjust the sizes of the MOS transistors to find a code thatresults in the smallest error. Then, the sizes of the MOS transistorsare increased or reduced, and this code is provided to the outputbuffer.

[0011] However, with this method, the circuit is affected by variousvariation factors such as a variation in reference voltage, an inputoffset voltage at the operational amplifier, a variation in the currentratio of a current source composed of the P channel MOS transistors, anda variation in MOS resistance. Thus, actually, it is difficult toaccurately adjust the output impedance.

[0012] For example, if the current ratio of the current source composedof the P channel MOS transistors varies by about 5%, this mere variationcauses the output impedance to reach the limit of the allowablevariation range of 45Ω±5Ω. Thus, disadvantageously, yield decreases andmuch labor is required to manage manufacturing steps. Therefore, inreality, it is difficult to accurately adjust the output impedance.

[0013] A second example of the prior art is Non-patent Document 2(ESSCIR2001 “Digitally tuneable on-chip line termination resistor for2.5 Gbit/s LVDS receiver in 0.25 μm standard CMOS technology” M. Kumric,F. Ebert, R. Rap, K. Welch Alcatel SEL Stuttgart (http://www. esscirc.org/esscirc2001/C01_Presentations/98.pdf)).

[0014] In Non-patent Document 2, as shown in FIG. 3, a value for aninternal trimming resistor is switched so that the externally providedreference voltage Vref is closest to a divided voltage resulting from anexternal resistor and the internal trimming resistor. Then, switchingcodes are used to switch input terminal resistance.

[0015] As shown in FIG. 4, the internal trimming resistor is composed ofa resistor R0 connected directly between IP and IN and resistors R1 toR8 each connected via a switch turned on and off in a controlled mannerusing a code.

[0016] As shown in FIG. 5, in consideration of the range of a variationin the value for the internal resistor, a value for the resistor R0 ispreset at a larger value. The resistors R1 to R8 are sequentiallyconnected together to adjust the value for the internal trimmingresistor over a wide range so that it falls within the range of astandard value of 100Ω±10Ω.

[0017] However, this method requires an external circuit used togenerate the reference voltage Vref as well as two external accurateresistors. This advantageously increases costs. Further, this method isused only for an input terminal section. The adjustment of the outputimpedance must include the adjustment of the on resistance of the outputbuffer as shown in the first example of the prior art.

[0018] A third example of the prior art is Patent Document 1.

[0019] In Patent Document 1 (Jpn. Pat. Appln. KOKAI Publication No.2001-94048), as shown in FIG. 6, the operational amplifier is used toadjust a current from the current source composed of the P channel MOStransistors so that a voltage drop VZQ at an external resistor PQ ishalf the voltage at a power source VDDQ. Further, the size of an outputdriver is adjusted by using a current mirror to allow a current to flowthrough the output driver so that the resulting voltage drop equals theVZQ.

[0020] In this case, a variation in output resistance is affecteddirectly by factors such as the offset voltage at the operationalamplifier and a variation in current mirror current. Consequently,accurate adjustment of the current is limited.

[0021] It has thus been strongly desirable to provide an impedancetrimming circuit which eliminates the adverse effects of variationsassociated with an LSI manufacturing process to accomplish accuratetrimming and which can be constructed using a reduced number of externalparts.

BRIEF SUMMARY OF THE INVENTION

[0022] According to an aspect of the present invention, there isprovided an impedance trimming circuit comprising a common bias sectioncomposed of a first series circuit having a first internal resistor andan external resistor connected in series via a first node and a firstoperational amplifier having a first input terminal connected to aninternal reference voltage, a second input terminal connected to thefirst node, and an output terminal connected to the first seriescircuit; and an impedance trimming section composed of a second seriescircuit having a second internal resistor and an impedance dummyresistor connected in series via a second node, a comparator having afirst input terminal connected to the first node and a second inputterminal connected to the second node, a code control circuit which usesa clock signal to latch an output signal from the comparator to generatea plurality of switching codes, and a switching circuit which uses theplurality of switching codes to switch a resistance value of theimpedance dummy resistor, wherein the first operational amplifier isalso connected to the second series circuit, and an output signal fromthe code control circuit is input to a target impedance trimmingresistor.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0023]FIG. 1 is a diagram showing a conventional impedance trimmingcircuit;

[0024]FIG. 2 is a diagram showing a conventional impedance trimmingcircuit;

[0025]FIG. 3 is a diagram showing a conventional impedance trimmingcircuit;

[0026]FIG. 4 is a diagram showing an example of a conventional trimmingresistor;

[0027]FIG. 5 is a diagram showing the relationship between codes and theresistance value of the trimming resistance;

[0028]FIG. 6 is a diagram showing a conventional impedance trimmingcircuit;

[0029]FIG. 7 is a diagram showing an impedance trimming circuitaccording to a first embodiment;

[0030]FIG. 8 is a graph showing the relationship between codes andoutput impedance;

[0031]FIG. 9 is a graph showing the results of simulation using SPICE;

[0032]FIG. 10 is a diagram showing an example of a code control circuitand an impedance dummy resistor;

[0033]FIG. 11 is a diagram showing waveforms observed during impedanceadjustment;

[0034]FIG. 12 is an impedance trimming circuit according to a secondembodiment;

[0035]FIG. 13 is an impedance trimming circuit according to a thirdembodiment;

[0036]FIG. 14 is a graph showing the relationship between codes andoutput impedance according to a fourth embodiment;

[0037]FIG. 15 is a diagram showing an impedance trimming circuitaccording to a fifth embodiment;

[0038]FIG. 16 is a graph showing the relationship between codes and theresistance value of an impedance dummy resistor;

[0039]FIG. 17 is a graph showing the relationship between the codes andthe resistance value of the impedance dummy resistor;

[0040]FIG. 18 is a timing chart of the operation of the circuit shown inFIG. 7;

[0041]FIG. 19 is a view showing an impedance trimming circuit as areference example;

[0042]FIG. 20 is a timing chart of the operation of the circuit shown inFIG. 19;

[0043]FIG. 21 is a timing chart of the operation of the circuit in FIG.19;

[0044]FIG. 22 is a view showing the output impedance trimming circuitaccording to the ninth embodiment;

[0045]FIG. 23 is a view showing an example of a code flattening circuit;

[0046]FIG. 24 is a timing chart of the operation of the circuit shown inFIG. 22;

[0047]FIG. 25 is a timing chart of the operation of the circuit in FIG.22;

[0048]FIG. 26 is a timing chart of the operation of the circuit in FIG.22;

[0049]FIG. 27 is a timing chart of the operation of the circuit in FIG.22;

[0050]FIG. 28 is a view showing the input impedance trimming circuitaccording to the ninth embodiment;

[0051]FIG. 29 is a view showing the input/output impedance trimmingcircuit according to the ninth embodiment;

[0052]FIG. 30 is a view showing base elements in the impedance trimmingcircuit according to an example of the present invention; and

[0053]FIG. 31 is a view showing base elements in the impedance trimmingcircuit according to another example of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0054] With reference to the drawings, description will be given of animpedance trimming circuit according to an example of the presentinvention.

[0055] 1. Outline

[0056] First, the impedance trimming circuit according to the example ofthe present invention has a common bias circuit composed of a referencevoltage circuit, an internal resistor R1, an accurate external resistorRext, and an operational amplifier OP1, and an output impedance trimmingcircuit composed of another internal resistor Rto, a driver dummyresistor Rdrv, an output impedance dummy resistor Rto_trim, anoperational amplifier OP1, a comparator CMP, and a code control circuit.

[0057] The following definitions are assumed: the resistance value ofthe internal resistor is defined as R1, the resistance value of theaccurate external resistor is defined as Rext, the resistance value ofthe second internal resistor is defined as Rto, the resistance value ofthe driver dummy resistor is defined as Rdrv, and the resistance valueof the output impedance dummy resistor is defined as Rto_trim. Then, thevalue Rto_trim is switched so as to establish the relationship shownbelow or the relationship closest to it.

Rext:R 1=(Rdrv+Rto_trim): Rto

[0058] Then, a driver circuit is allowed to reflect this switchinginformation.

[0059] The impedance trimming circuit according to the example of thepresent invention further has an input impedance trimming circuitcomposed of another internal resistor Rti, an input impedance dummyresistor Rto_trim, an operational amplifier OP2, a comparator CMP, and acode control circuit. A resistance value of this third internal resistoris defined as Rti, and the resistance value of the input impedance dummyresistor is defined as Rti_trim. Then, the value Rti_trim is switched soas to establish the relationship shown below or a relationship closestto it.

Rext:R 1=Rti_trim:Rti

[0060] Then, an input impedance circuit is allowed to reflect thisswitching information

[0061] The impedance trimming circuit has only to have at least one ofthe output impedance trimming circuit and the input impedance trimmingcircuit. Further, if only the output impedance trimming circuit or inputimpedance trimming circuit is used or if both impedance trimmingcircuits are used, a plurality of impedance trimming circuits of eachtype may be present.

[0062] 2. First Embodiment

[0063]FIG. 7 shows an impedance trimming circuit according to a firstembodiment of the present invention.

[0064] Reference character Rdrv (symbol Δ) denotes an output driver. Acommon bias section 11 has the internal resistor R1 and accurateexternal resistor Rext connected together via a node Vr1, theoperational amplifier OP1 to which an internal reference voltage Vrefand the voltage at the node Vr1 are inputted, a P channel MOS transistorP1, and an N channel MOS transistor N1. The P channel MOS transistor P1,connected to a power source VDD, is a bias generating circuit used togenerate a small-current bias provided to another circuit. This is anaccessory circuit.

[0065] Operations of this circuit will be described below with referenceto FIG. 7.

[0066] The operational amplifier OP1 controls a gate voltage of the Nchannel MOS transistor (current control element) N1 so that the voltageVr1 equals the internal reference voltage Vref. The voltage Vr2 is thevoltage Vr1 plus a voltage drop at the resistor R1 with a current I1,i.e. Vr2=Vr1+(R1/Rext)×Vr1.

[0067] A specific example of calculation will be shown below.

[0068] The internal reference voltage Vref is assumed to be, forexample, 1.2 V±5%. The external resistor Rext is assumed to offer anaccurate resistance of, for example, 12 KΩ±0.1%. The power voltage VDDis assumed to be, for example, 3.3 V±10%. The offset voltage at theoperational amplifier OP1 is assumed to be, for example, ±10 mV.

[0069] A negative feedback circuit composed of the operational amplifierOP1 and the N channel MOS transistor (current control element) N1operates to make a value for a voltage drop at the external resistorRext equal to the internal reference voltage Vref. As a result, Vr1becomes Vref. The accuracy is (1.2 V±5%)±10 mV, i.e. 1.2 V±0.07 V owingto the effects of a variation in internal reference voltage Vref and theoffset voltage at the operational amplifier OP1.

[0070] The current I1 is equal to Vr1/Rext. The current I1 also variesand is within the range of, for example, 100 μA±7 μA. A voltage Vr2 isaffected directly by a variation in a value for the internal resistorR1. If the variation in the value for the internal resistor R1 is, forexample, 2.4 KΩ±20%, then the voltage Vr2 is given as follows:$\begin{matrix}{{Vr2} = {{Vr1} + {{I1} \times {R1}}}} \\{= {\left( {{1.2\quad V} \pm {0.07\quad V}} \right) + {\left( {{100\quad {µA}} \pm {7\quad {µA}}} \right) \times \left( {{2.4\quad {k\Omega}} \pm {0.48\quad {k\Omega}}} \right)}}} \\{= {{1.44\quad V} \pm {0.13\quad V}}}\end{matrix}$

[0071] Importantly, the voltage Vr2 corresponds to the detection of aratio containing a difference in resistance value between the internalresistor R1 and the external resistor Rext.

[0072] Now, description will be given of an output impedance trimmingsection 12.

[0073] The output impedance trimming section is composed of thecomparator CMP to which the voltage Vr1 and a voltage Vto1 are inputted,an operational amplifier OP2 to which the voltage Vr2 and a voltage Vto2are inputted, a code control circuit 13 that receives an output signalfrom the comparator CMP, an N channel MOS transistor (current controlelement) N2, the internal resistor Rto, the output impedance dummyresistor Rto_trim, and the output driver dummy resistor Rdrv.

[0074] The operational amplifier OP2 controls a gate voltage of the Nchannel MOS transistor N2 so that the voltage Vto2 equals the voltageVr2. In this condition, the voltage Vto1 is divided into Rto and(Rto_trim+Rdrv). However, importantly, the ratio of Rext to R1 is equalto the ratio of Rto_trim+Rdrv to Rto.

Rext:R 1=(Rto_trim+Rdrv):Rto

[0075] The value for the external resistor Rext is accurate. Thus, evenif the value for the internal resistor R1, Rto, Rto_trim, or Rdrvvaries, the value Rto_trim+Rdrv can generally be accurately brought intothe range of a standard value by manufacturing a circuit so that R1 andRto have a good relative accuracy.

[0076] The code control circuit 13 is composed of, for example, amultistage shift register. An output from the comparator CMP, a resultof a comparison of Vr1 with Vto1, is inputted to the multistage shiftregister that carries out a shifting operation on the basis of a clocksignal CLK. A code is obtained from each stage of the shift register toswitch among the resistors. To switch among the resistors, it ispossible to use, for example, the circuit shown in the second example ofthe prior art.

[0077] Then, as the clock signal CLK is supplied many times, the stateis established where the relationship between the potentials Vr1 andVto1 exhibits the most frequent switching between a positive side and anegative side, i.e. the potentials Vr1 and Vto1 have the closest valuesthat vary between the positive side and the negative side or where thecode is stopped and stabilized. This state corresponds to a code withwhich the value Rto_trim+Rdrv is closest to the standard.

[0078] A specific example of a calculation will be shown below.

[0079] If the offset voltage at the operational amplifier is, forexample, ±10 mV, then the following equation is given; $\begin{matrix}{{Vto2} = {{Vr2} \pm {10\quad {mV}}}} \\{= {{{1.44\quad V} \pm {0.13\quad V}} \pm {10\quad {mV}}}} \\{= {{1.44\quad V} \pm {0.14\quad V}}}\end{matrix}$

[0080] A current value Ito is equal to Vto2/(Rto+Rto_trim+Rdrv).

[0081] Because of the current Ito, Vto1 has the following voltageeffects:

Vto 1=Ito 1×(Rto_trim+Rdrv)

[0082] Consequently, the following equation is established:$\begin{matrix}{{Vto1} = {{{Vto2}/\left( {{Rto} + {Rto\_ trim} + {Rdrv}} \right)} \times \left( {{Rto\_ trim} + {Rdrv}} \right)}} \\{= {{Vto2}/\left( {1 + {{Rto}/\left( {{Rto\_ trim} + {Rdrv}} \right)}} \right)}}\end{matrix}$

[0083] Vto2 is determined by the ratio of Vto2 to resistance.

[0084] The comparator CMP selects Rto_trim so that Vr1 is closest toVrto1. Accordingly, on this occasion, if the offset voltage at thecomparator CMP is defined as Voffcmp (±20 mV), then the followingequation is given:

Vto 1=Vr 1±Voffcmp

[0085] Specifically, the right side=1.2 V±0.07 V±0.02 V=1.2 V±0.09 V.

[0086] If the right side equals the left side Vto1, then the followingequation is established:

1.2V±0.09V=(1.44V±0.14V)/(1+Rto/(Rto_trim+Rdrv)

[0087] Here, it is assumed that the output impedance trimming circuitcomposed of Rto and (Rto_trim+Rdrv) offers resistance that is, forexample, six times as large as that of an actual output buffer circuitin order to reduce current consumption. Accordingly, if an actual driveroutput impedance is to be 45Ω, then Rto_trim+Rdrv is 270Ω.

[0088] Rto is 54Ω on the basis of the relationshipRext:R1=(Rto_trim+Rdrv):Rto, i.e. 12 KΩ:2.4 K=270Ω:54Ω.

[0089] Further, it is assumed that Rto_rim+Rdrv=270Ω, Rto_trim=240Ω, andRdrv=30Ω.

[0090] Importantly, the resistors R1 and Rto are formed within the sameintegrated circuit and can thus be manufactured so as to have a goodrelative accuracy. Further, the resistor Rto_trim can also bemanufactured so as to have a good relative accuracy. However, since theresistor Rdrv is composed of, for example, a MOS transistor, itsvariation contains a variation associated with the manufacture of thetransistor.

[0091] This is substituted into the previous equation.

1.2V±0.09V=(1.44V±0.14V)/(1+(Rto/(Rto_trim+Rdrv))

[0092] Then, the following equation is established:

Rto/(Rto_trim+Rdrv) =((1.44V±0.14V)/(1.2V±0.09V))−1

[0093] Accordingly, the adjusted resistance value Rto_trim is written onthe left side, the following equation is given:

Rto_trim=(Rto/((1.44V±0.14V)/(1.2V±0.09V))−1)−-Rdrv

[0094] Specific values are substituted into the above equations.

[0095] If the following assumptions are made:

Rdrv=30Ω±20Ω,

Rto=54Ω±10.8Ω

[0096] then the following equation is given:

Rto_trim=((54Ω±10.8Ω)/((1.44V±0.14V) /(1.2V±0.09V)−1))−(30Ω±20Ω)

[0097] If a center condition is used for all cases, then the followingcalculation can be executed:

Rto_trim(center)=(54Ω/((1.44V/1.2V)−1))−30Ω=240Ω

[0098] That is, if Rto_trim is adjusted to be closest to 240Ω, the finalvalue is determined to be 240Ω. If the value for the resistor Rdrvconnected in series with the resistor Rto_trim is added to this finalvalue, then 30Ω+240Ω=270Ω. Thus, the resistance is accurately adjustedto a value that is six times as large as the target one, i.e. 45Ω.

[0099] Variations in various factors can be determined using the abovecalculation. However, this requires various calculations and theirdescription is thus omitted. An important point is that a wide range ofvariation is assumed so that the value for the output impedance dummyresistor Rto_trim can be adjusted over a wide range.

[0100]FIG. 8 shows an example of an adjustment range for the trimmingcircuit.

[0101] Actually, under the same conditions as those for the drivercircuit, too large a current may flow. Thus, to limit the current, thevalue for the output impedance dummy resistor Rto_trim is designed to beabout six times as large as the target value. Table 1, shown below,shows this value in terms of the impedance of the output driver. TABLE 1Rtrm 53.33 *0.8 *1.2 *0.9 *1.1 Rsw 5 3 8 3 8 Code Typ (−20%) (+20%)(−10%) (+10%) 0 58.33 45.67 72.00 51.00 66.67 1 53.70 41.96 66.43 46.8361.57 2 40.80 38.84 61.76 43.32 57.28 3 46.48 36.19 57.78 40.33 53.63 443.62 33.90 54.34 37.76 50.48 5 41.13 31.90 51.35 35.53 47.74 6 38.9430.15 48.73 33.55 45.33 7 37.00 28.60 46.40 31.80 43.20

[0102] This table shows how the output impedance of the actual drivervaries when the code control circuit 13 is switched among eight statesobtained by constructing the code control circuit 13 using a 7-stageshift register.

[0103] This graph contains the range of a variation and is based on theassumptions that Rto_trim is 20% and that a switch required forswitching operations offers resistance 5Ω+3Ω/−2Ω.

[0104] For calculations, it is assumed that the resistance value of eachswitch=5Ω, R1, . . . R7=560Ω, and the driver resistance Rdrv=5Ω.

[0105] In consideration of a variation in the value for the internalresistor, Rto_trim+Rdrv is set so as to be arbitrarily switched within acertain range around a target value (in this case, 45Ω) using codes.

[0106] For example, for the driver circuit, Rto+Rdrv is set to be 58.33Ωat maximum and 37Ω at minimum. Cases indicated by *0.8 and *1.2 areexamples of calculations that take various variations or dependenciesinto consideration. Under a standard condition, the optimum value of 45Ωlines between codes 3 and 4. However, under the best condition indicatedby *0.8, the optimum value is found between codes 0 and 1. Under theworst condition indicated by *1.2, the optimum value is found betweencodes 6 and 7.

[0107] It is evident that even if the standard value is set at 45Ω±5Ω,the value can be adjusted even with a variation of ±20% in the value forthe internal resistor.

[0108] Consequently, Vt1≈Vto2, Ito, and others are controlled so thatVr1 equals Vto1. Therefore, the values including Vref are onlyintermediate variables for a control system the final result of which isan accurate resistance ratio. It is thus evident that direct effectshave been eliminated.

[0109] Furthermore, importantly, although not shown in detail, thepresent circuit is very insensitive to Vref, the offset voltage at theoperational amplifier OP1, a variation in current, and the like. Theresistance ratio of R1 to Rto must be accurate, but a relative accuracyof ±0.5% or less can be easily accomplished by arranging these resistorsso as to occupy a certain area or larger in the LSI and to lie close toeach other.

[0110]FIG. 9 shows the results of circuit simulation using SPICE exceptfor the impedance trimming circuit Rtrim.

[0111] In this figure, the axis of ordinate indicates Vto1 to Vr1, aninput to the comparator CMP, while the axis of abscissa indicates theelapsed time from 0 to 10 μs. This figure shows the results ofsimulation obtained by linearly varying the value Rtrim. Even if theranges of variations described above are combined together 100 timesusing a Monte Carlo method, all lines other than the lower two cross a0-V line. This indicates the possibility of adjustment.

[0112]FIG. 10 shows an embodiment of the control circuit and impedancedummy resistor.

[0113] A code control circuit 13 comprises, e.g., a seven-stage shiftregister. An impedance dummy resistor Rto trim comprises a resistor R1and seven series elements connected in parallel with the resistor R1.Each of the series elements comprises a resistor R and a switch SW.

[0114] It should be noted that the resistance values of the resistors Rand R1 are denoted by Rtrm. Also, the resistance values of the resistorsR and R1 which are measured when the respective switches are turned onare denoted by Rsw. The following explanation will be given on thesupposition that Rsw is 0.

[0115] In this embodiment, the number of code control signals (codevalues) is eight. For example, they are 0 to 7. To be more specific,when all the output signals a, b, . . . g of the code control circuit 13are “L” (=“0”), e.g., the code value is 0, all the switches SW areturned off, and the resistance value of the impedance dummy resistor Rtotrim is equal to Rtrm.

[0116] When one of the output signals a, b, . . . g of the code controlcircuit 13 is “H” (=“1”), e.g., the code value is 1, one of the switchesSW is turned on, and the resistance value of the impedance dummyresistor Rto trim is Rtrm/2.

[0117] In such a manner, with respect to the output signals a, b, . . .g of the code control circuit 13, the impedance dummy resistor Rto trimvaries within a range from Rtrm to Rtrm/(K+1) in accordance with thenumber of signals indicating “1”.

[0118] In the circuit according to the above embodiment, when Vto1>Vr1,the comparator shown in FIG. 1 continuously outputs “1”. The output “1”from a comparator CMP synchronizes with a clock signal CLK. The stagesof the shift registers successively receive the output “1”. That is,when Vto1>Vr1, the number of those of the output signals a, b, . . . gof the code control circuit 13, which indicate “1”, increases bydegrees.

[0119] To be more specific, the code value increases by degrees, thenumber of switches SW which are in the ON state increases by degrees,and the resistance value of the impedance dummy resistor Rto trim lowersby degrees.

[0120] On the other hand, when Vto1<Vr1, the comparator in FIG. 1outputs “0”. The output “0” synchronizes with the clock signal CLK. Thestages of the shift register successively receives the output “0”. Then,when a predetermined time period lapses, and “1” input to the firststage of the shift register is output from the last stage thereof, thecode value decreases, the number of switches SW which are in the ONstate decreases, and the resistance value of the impedance dummyresistor Rto trim increases.

[0121] Thereafter, the code value repeatedly varies between a value atwhich “Vto1>Vr1” is satisfied and a value at which “Vto1<Vr1” issatisfied (periodic variation). This applies to a case where the codevalue varies by a 1-bit width (between two values). In a case where thecode value varies by a two-bit width (between three values), itrepeatedly varies between a value at which “Vto1≧Vr1” is satisfied and avalue at which “Vto1≦Vr1” is satisfied.

[0122] In the above manner, the code value is set to be optimal. Whenall the values of the stages of the shift register are “1”, i.e., allthe resistors R1 are electrically connected in parallel, and then whenVto1≧Vr1, the code value is determined in this state (it is set at themaximum value “7”). When all the values of the stages of the shiftregister are “0”, i.e., the highest resistance value is set (only theresistance value of a resistor R1 is used), and then when Vto1≦Vr1, thecode value is determined in this state (it is set at the minimum value“0”).

[0123] The operational waveform diagram in FIG. 11 indicates thisadjustment.

[0124] This figure shows how the state changes.

[0125] 3. Second Embodiment

[0126]FIG. 12 shows an impedance trimming circuit according to a secondembodiment of the present invention.

[0127] This embodiment relates to an input impedance trimming circuit14. Compared to the above output impedance trimming circuit, thiscircuit does not require any driver dummy resistors or drivers butsimply trims resistance and uses the code obtained to adjust the inputimpedance.

[0128] Operations of this circuit are the same as those in the firstembodiment. Their description is thus omitted.

[0129] 4. Third Embodiment

[0130]FIG. 13 shows an impedance trimming circuit according to a thirdembodiment of the present invention.

[0131] This embodiment relates to an I/O impedance trimming circuit.This circuit has the output impedance trimming section 12 and the inputimpedance trimming section 14. In this case, a single common biassection 11 can be shared by the output impedance trimming section 12 andthe input impedance trimming section 14.

[0132] Operations of this circuit are the same as those in the firstembodiment. Their description is thus omitted.

[0133] 5. Fourth Embodiment

[0134]FIG. 14 shows an impedance trimming circuit according to a fourthembodiment of the present invention.

[0135] This embodiment relates to a resistance adjustment circuit.

[0136] With the method shown in the second example of the prior art, theimpedance is adjusted by connecting the resistor R0 in parallel with theresistors R1 to R8 having the same resistance value as the resistor R0.However, this method is disadvantageous in that the number of codeincreases with the allowable variation range and that it is necessary toswitch the resistance over a wide range from smaller to largerresistance.

[0137] In this embodiment, the relationship between the code and theresistance value is represented by an S-shaped curve or a polygonalline. Accordingly, even with a wide range of variation, the impedancecan be adjusted using a small number of codes.

[0138] Specifically, for example, in the second example of the priorart, the value for the resistor R0 is set at 55Ω. The value for theresistors R1 and R2 is set at 67Ω. The value for the resistors R3, R4,and R5 is set at 100Ω. The value for the resistor R6 is set at 42Ω. Thevalue for the resistor R7 is set at 33Ω. In this manner, the differentresistance values are used for the respective resistors so that therelationship between the code and the resistance value is represented byan S-shaped curve or a polygonal line.

[0139] In this regard, a decode circuit may be provided which serves tochange the resistance values used for adjustment. Rather than usingsimple shift registers for switch control, this decode circuit detectsthe number of level 1 on the basis of an output from each stage of themultistage shift register, to select resistors to be connected inparallel on the basis of this number.

[0140] 6. Fifth Embodiment

[0141]FIG. 15 shows an impedance trimming circuit according to a fifthembodiment of the present invention.

[0142] This embodiment relates to a resistance adjustment circuit and isan applied example of the resistance adjustment shown in the firstembodiment.

[0143] The LSI has the following parasitic resistances: lead frameresistance, bonding wire resistance, intra-pellet wiring resistance, andthe like, which are parasitic on a package. Thus, from the outside ofthe package, the impedance of the LSI appears like a series connectionof all these resistances. In this embodiment, all these parasiticresistances are estimated before the value for the impedance dummyresistor Rtrim is adjusted. Then, the impedance is adjusted to exhibit adesired value with all parasitic resistances present.

[0144] For example, if wiring resistance Rmetal is 0.5Ω, bonding wireresistance Rbdg is 0.3Ω, and lead frame resistance Rfrm is 0.2Ω, thenthe resistance of the whole current path from power pin to output pin ofthe buffer is 2×(0.5Ω+0.3Ω+0.2Ω)=2Ω.

[0145] In such a case, the impedance dummy resistance Rtrim may beadjusted to a value smaller than the desired resistance value, 45Ω, byabout 2Ω, i.e. 43Ω. However, with the present circuit, it is cumbersometo switch the value for the impedance dummy resistor Rtrim around thisvalue, 43Ω.

[0146] In this embodiment, the adjustment range of the value for theimpedance dummy resistor Rtrim can be shifted by switching the value forthe resistor R1.

[0147] If Rext:R1=Rtrim:Rt and Rtrim is to be changed from 45Ω to 43Ωfor adjustment, the value R1 may be increased by a value of 45/43. Inthis case, to allow the value R1 to be switched with all expectedparasitic resistances taken into account, an LSI pattern may be providedbefore the value R1 is increased or reduced. A switching operation maybe performed by using an analog switch, switching the metal layer usinga master slice, or using other methods.

[0148]FIGS. 16 and 17 show an example of a variation in resistance withrespect to the code observed if the value for the impedance dummyresistor Rtrim is switched with the parasitic resistances taken intoaccount.

[0149] As shown in these figures, if the parasitic resistances aresmall, the value for the impedance dummy resistor Rtrim can be switchedaround a larger value, e.g. 43Ω. On the other hand, if the parasiticresistances are large, the value for the impedance dummy resistor Rtrimcan be switched around a smaller value, e.g. 40Ω.

[0150] Even with a different package, the impedance can be kept constantaccording to this embodiment.

[0151] 7. Sixth Embodiment

[0152] Now, description will be given of an impedance trimming circuitaccording to a sixth embodiment of the present invention.

[0153] This embodiment is a variation of the above described fifthembodiment. Specifically, in FIG. 15, the value for the accurateresistor Rext need not necessarily be singular. For example, if theaccurate resistor Rext has a resistance value of 12 kΩ, the value forthe resistor R1 is set at 2.4 kΩ. On the other hand, if the accurateresistor Rext has a resistance value of 13 kΩ, the value for theresistor R1, 2.4 kΩ, may be increased by (13/12)×2.4 kΩ up to 2.6 kΩ.

[0154] Operations of this circuit are omitted, but the relationshipRext:R1=Rtrim:Rt is maintained.

[0155] Thus, the impedance can be kept constant even with a change inthe value for the accurate resistor Rext.

[0156] 8. Seventh Embodiment

[0157] Now, description will be given of an impedance trimming circuitaccording to a seventh embodiment of the present invention.

[0158] This embodiment is a combination of the above described fifth andsixth embodiments. When the fifth and sixth embodiments are thuscombined together, the resistance value of the resistor R1 can beswitched to correct the resistance value of the accurate resistor Rextand the values for various resistances parasitic on the package. Thatis, the impedance can be kept constant even with a change in the valuefor the accurate resistor Rext or in the type of the package.

[0159] 9. Eighth Embodiment

[0160] Now, description will be given of an impedance trimming circuitaccording to an eighth embodiment of the present invention.

[0161] This embodiment relates to measures taken if the internalreference voltage Vref deviates from the desired value in the abovedescribed fifth embodiment. For example, it is assumed that the targetvalue for the internal reference value is 1.2 V and that the value forthe accurate resistor Rext is 12 kΩ. In this case, a current flowingthrough the accurate resistor Rext is Vref/Rext=100 μA.

[0162] Here, the internal reference voltage Vref may deviate from 1.2 Vowing to a change in manufacturing process or the like. If the internalpower voltage Vref becomes 1.25 V, then a current of 125 μA flowsthrough the accurate resistor Rext. The voltage Vr2 also increases witha voltage drop at the resistor R1.

[0163] In such a case, the resistor R1 is divided into two parts, andthe midpoint between these parts is defined as Vr1 and connected to anegative input terminal of the operational amplifier OP1. Then, apotential difference of 1.25 V−1.2 V=0.05 is absorbed by one (the lowerpart of R1) of the two parts which is connected to the accurate resistorRext. Further, the other part (the upper part of R1) connected to anoutput terminal of the operational amplifier OP1 has a resistance valuethat meets the relationship Rext:(lower part of R1+upper part ofR1)=Rtrim:Rt.

[0164] Thus, according to the present embodiment, even with a variationin internal reference voltage Vref, the operational current can be keptconstant. Therefore, the value Rtrim can be accurately adjusted.

[0165] 10. Ninth Embodiment

[0166] The impedance trimming circuit according to the ninth embodimentof the present application will be explained.

[0167] (1) The impedance trimming circuit according to the ninthembodiment is provided based on the following premise

[0168] The above impedance trimming circuits according to the first toeighth embodiments execute impedance matching with respect to the outputimpedance, input impedance, terminal resistance or the like, to therebysuppress reflection of signals, thus allowing serial signals to betransferred at a high speed while maintaining their high quality, andautomatically perform such trimming at a high accuracy.

[0169] However, for example, the output impedance trimming circuit shownin FIG. 7 performs trimming of the output impedance, with the outputsignal of the code control circuit 13 kept as it is. Thus, shown in FIG.18, when Vto1 becomes close to Vr1, it repeatedly increases anddecreases with respect to Vr1.

[0170] As a result, the value of the impedance dummy resistor Rto trimof the output impedance trimming circuit in FIG. 7 continuously variesduring trimming of the output impedance. This variation may affect theoperation of the circuit.

[0171] Similarly, for example, the input impedance trimming circuitshown in FIG. 12 performs trimming of the input impedance, with theoutput signal of the code control signal 13 kept as it is. Thus, thesame phenomenon as in the circuit in FIG. 18 occurs. That is, Vtil doesnot constantly vary. As a result, the value of the input impedance dummyresistor Rti trim of the input impedance trimming circuit in FIG. 12also continuously varies during trimming of the input impedance.

[0172] Furthermore, shown in FIG. 18, when Vto1 varies by a two-bitwidth with respect to Vr1, e.g., Vto1 varies between “2” and “4”, it isclosest to Vr1 when it is “3”. Thus, in such a case, trimming can beexecuted at a high accuracy by fixing the code value which controls theimpedance, at a value at which Vto1 is “3”, i.e., the central value ofthe variation range of Vto1. The same is true of Vti1.

[0173] It can be therefore found by considering the above that when Vto1or Vtil reaches a value close to Vr1 which is a target value, it isappropriate that the input and output impedance dummy resistors Rto trimand Rti trim be fixed at predetermined values, i.e., the output signalof the code control signal 13 be fixed at a predetermined value.

[0174] Then, it should be noted that, for example, the impedancetrimming circuit disclosed in patent document 2 (Jpn. Pat. Appln. KOKAIPublication No. 2003-69412) is used as an impedance trimming circuitwhich latches the value of the output signal of a code control circuit.

[0175]FIG. 19 shows a main portion of the impedance trimming circuitdisclosed in patent document 2. The points of this circuit will bedescribed below, but its detailed explanation will be omitted.

[0176] The first point of the impedance trimming circuit in patentdocument 2 resides in that trimming of the impedance is carried outwithout using an external resistor by a current source 215 provided in achip, unlike the impedance trimming circuit of the present invention.The second point of the impedance trimming circuit of patent document 2resides in that when Vtarget reaches to a value close to Cref, a thermalcode Cli corresponding to the code of the impedance trimming circuit ofthe present invention is fixed.

[0177] However, in the impedance trimming circuit of patent document 2,when Vtarget is greater than Vref as shown in, e.g., a timing chart ofFIG. 20, a U/D signal becomes “H”, and when the number of times Vtargetexceeds Vref reaches two, i.e., the U/D signal becomes “H” twice, thetime at which the U/D signal varies from “H” to “L” after becoming “H”twice is detected by a control circuit 211, and then a signal COMPLETEis set at “H”, and the value of the thermal code C1 i is fixed. Thus,when the signal COMPLETE is set at “H”, Vtarget does not coincide withthe central value (Vref) of its variation range, as a result of whichtrimming cannot be performed with a high accuracy.

[0178] Therefore, the impedance trimming circuit according to the ninthembodiment, which will be explained below, fixes a code value for use inimpedance trimming at a high speed at a value at which Vto1 or Vtil isclosest to Vr1 (Vto1=Vr1 or Vti1=Vr1 if Vto1 or Vtil varies by a two-bitwidth with respect to Vref), when Vto1 or Vtil reaches a value close toVtil which is a target value.

(2) EXAMPLE 1

[0179]FIG. 22 shows example 1 of the impedance trimming circuitaccording to the ninth embodiment of the present invention.

[0180] Rdrv (symbol Δ) denotes an output driver.

[0181] A common bias section 11 includes an internal variable resistorR1a connected via a node Vr1, a precision external resistor Rext, anoperational amplifier OP1 to which an internal reference voltage Vrefand a voltage of the node Vr1 are to be applied, P-channel MOStransistors P1 a and P1 b, and an N-channel MOS transistor N1. TheP-channel MOS transistor Pla and P1 b are connected to a power supplyVDD. These transistors are bias generating circuits for generating aconstant-current bias, and also accessory circuits.

[0182] Explanations for the operation of the common bias section 11 andan example of the operation will be omitted, since they are the same asthose of the common bias section shown in FIG. 7.

[0183] The output impedance trimming section 12 comprises a comparatorCMP to which voltages Vr1 and Vto1 are to be applied, an operationalamplifier OP2 to which voltages Vr1 and Vto2 are to be applied, a codecontrol circuit 13 which receives the output signal of the comparatorCMP, an N-channel MOS transistor (current control element) N2, aninternal resistor Rto, an output impedance dummy resistor Rto trim, andan output driver dummy resistor Rdrv.

[0184] The operational amplifier OP2 controls the gate voltage of theN-channel MOS transistor N2 such that the voltage Vto2 is equal to thevoltage Vr2. In this state, the voltage Vto1 is determined by the ratiobetween resistors Rto and Rto trim+Rdrv. It is important that the ratioof Rext to R1 is equal to that of Rto trim+Rdrv to Rto. That is:

Rext: R 1=(Rto trim+Rdrv): Rto

[0185] The external resistor Rext is highly accurate. Thus, even if themanufactured output impedance trimming sections are variant with respectto each of the resistors R1, Rto, Rto trim and Rdrv, in general, if therelative precision between the internal resistors R1 and Rto is high,the value of Rto trim+Rdrv can be made to fall within a standard range.

[0186] The code control circuit 13 comprises, e.g., a multistage shiftregister in which the code value varies in response to a clock signalCLK. The output of the comparator CMP which is obtained as a result ofcomparison between Vr1 and Vto1 is input to the multi-stage shiftregister. The figures of the code value are taken out from therespective stages of the shift register, and turning on/off of theresistors is switched. In order to switch turning on/off of theresistor, the second example of the prior art can be used.

[0187] Vto1 varies by degrees to reach Vr1 provided as a target value,in synchronism with the clock signal CLK. Then, when the relationshipbetween Vr1 and Vto1 repeatedly varies, i.e., Vto1 increases anddecreases with respect to Vr1, the code control circuit 13 outputs acode value at which Rto trim+Rdrv is closest to the standard value.

[0188] Explanations for the operation of the output impedance trimmingsection 12 and an example of the operation will be omitted, since theyare not greatly different from those of the output impedance trimmingsection shown in FIG. 7.

[0189] A code flattening section 15 includes a code flattening circuit16.

[0190] The code flattening circuit 16 receives the output signal (codevalue) of the code control circuit 13. The code flattening circuit 16outputs the output signal of the code control circuit 13 as an outputsignal SEL, as it is, when Vto1 always varies in one direction (e.g.,plus direction) toward Vr1. Then, when Vto1 is closest to Vr1, the codeflattening circuit 16 fixes the output signal (code value) of the codecontrol circuit 13 at a value at which Vto1 is closest to Vr1, andthereafter outputs the fixed code value as the output signal SEL.

[0191]FIG. 23 shows an example of the code flattening circuit.

[0192] A register 17 latches a code control signal (code value) outputfrom the code control circuit 13 shown in FIG. 22. To the register 17, adown detection signal DOWN is input. When the down detection signal DOWNbecomes “H”, the register 17 latches the code control signal.

[0193] A down detection signal generating circuit 18 synchronizes withthe clock signal CLK, fetches an up/down signal UP/DOWN, which isdisclosed in, e.g., FIG. 10, and outputs the down detection signal DOWNon the basis of the up/down signal UP/DOWN.

[0194] The example shown in FIG. 10 has the following circuit structure:when Vto1 is greater than Vr1, the up/down signal UP/DOWN becomes “H”(=“1”), and when Vto1 is smaller than Vr1, the up/down signal UP/DOWNbecomes “L” (=“0”).

[0195] In the example of FIGS. 22 and 23, it is considered that Vto1gradually increases from a condition satisfying Vto1<Vr1. Thus, in thoseexamples, the example of FIG. 10 is modified to achieve the followingcircuit structure: when Vto1 is smaller than Vr1, the up/down signalUP/DOWN becomes “H” (=“1”), and when Vto1 is greater than Vr1, theup/down signal UP/DOWN becomes “L” (−“0”). Such a circuit structure canbe easily achieved by modifying the comparator CMP.

[0196] In example 1, the up/down signal UP/DOWN becomes “H” (UP) whenVto1 is smaller than Vr1. This indicates that Vto1 increases toward Vr1,and thus the down detection signal is kept “L”.

[0197] On the other hand, the up/down signal UP/DOWN becomes “L” (DOWN)when Vto1 is greater than Vr1. This indicates that Vto1 exceeds Vr1.Thereafter, since Vto1 needs to be decreased, the down detection signalDOWN is made to be “H”.

[0198] Suppose that at the time of impedance trimming, Vto1 increases bydegrees toward Vr1, i.e., the target value, as stated above.

[0199] Needless to say, as a modification, suppose that Vto1 graduallydecreases toward Vr1 (target value), an up detection signal generatingcircuit for detecting that Vto1 increases may be provided as amodification of the down detection signal generating circuit 18. (Inthis case, the structure in FIG. 10 can be used as it is).

[0200] A multiplexor (MUX) 19 selects and outputs one of the outputsignal (code control signal) of the code control circuit 13 and theoutput signal of the register 17, which are shown in FIG. 22.

[0201] To be more specific, when the down detection signal DOWN is “L”,the multiplexor (MUX) 19 selects and outputs the output signal (codecontrol signal) of the code control circuit in FIG. 22. When the downdetection signal DOWN is “H”, the multiplexor (MUX) 19 selects andoutputs the output signal of the register 17.

[0202] That is, once the down detection signal DOWN becomes “H”, themultiplexor (MUX) 19 necessarily selects and outputs the output signalof the register 17.

[0203] A bit variation monitoring circuit 20 always monitors the codecontrol signal (code value), i.e., a bit value. Then, when the bit valuebecomes the maximum value (which is “7” in the case where the bit valuevaries from the range of “0” to “7”), the bit variation monitoringcircuit 20 outputs a predetermined value (e.g., “6”) as a bit value.

[0204] At this time, the bit variation monitoring circuit 20 outputs acontrol signal CT for use in controlling the operation of a multiplexor(MUX) 21, so that the multiplexer (MUX) 21 selects the output signal ofthe bit variation monitoring circuit 20.

[0205] In general, the bit variation circuit 20 is provided by a user'srequest. Thus, it may be omitted.

[0206] Next, the operation of the output impedance trimming circuitshown in FIGS. 22 and 23 will be explained.

[0207] First, the case where Vto1 periodically increases and decreaseswith respect to Vr1 will be explained by referring to the timing chartin FIG. 24.

[0208] In the initial state, Vto1 is far from Vr1. Thus, Vto1synchronizes with the clock signal CLK, and increases by degrees. Inorder that the operation be easily understood, in the followingexplanation, Vto1 is expressed by “0” to “7” to correspond to the codecontrol signal (the code value of which varies from the range of “0” to“7”) output from the code control circuit 13.

[0209] Under the above condition, since Vto1 continuously increases, thedown detection signal generating circuit 18 continuously maintains “L”as the value of, e.g., the down detection signal DOWN. At this time, theregister 17 does not latch the code control signal, and the multiplexor(MUX) 19 selects and outputs the code control signal from the codecontrol circuit 13.

[0210] Furthermore, since the value of the code control signal is notthe maximum value, the bit variation monitoring circuit 20 controls themultiplexor 21 such that the multiplexor 21 selects and outputs theoutput signal of the multiplexor 19.

[0211] When Vto1 is in the vicinity of Vr1, it repeatedly increases anddecreases with respect to Vr1. For example, in the example of FIG. 24,Vto1 repeatedly varies between “3” and “4”. That is, Vto1 varies by a1-bit width with respect to Vr1.

[0212] The code control circuit 13 outputs “L” (=“0”) as the up/downsignal UP/DOWN, when Vto1 varies to be greater than Vr1. When the downdetection signal generating circuit 18 in the code flattening circuit 16detects that the up/down signal UP/DOWN becomes “L”, it determines thatVto1 will decrease, and makes the down detection signal DOWN “H”.

[0213] The down detection signal generating circuit 18 may be formed tooutput the down signal (pulse signal) DOWN, when detecting a down edgeof Vto1 (variation from “4” to “3”).

[0214] When receiving the first down detection signal DOWN, the register17 latches “3” as the code control signal, and thereafter, does notaccept the input signal. At the same time, the multiplexor 19 selectsand outputs the output signal of the register 17, and thereafter, alwaysselects and outputs the output signal of the register 17.

[0215] In such a manner, when Vto1 is in the vicinity of Vr1, the codeflattening circuit 16 fixes the code control signal (code value) at avalue at which Vto1 is closest to Vr1, i.e., “3” in this example. Thus,in precision trimming of the example, the resistance value (code value)of a resistor Rto use for use in actual trimming of an output impedancecan be fixed at an optimal value at a high speed, and thus, it is notnecessary to consider the influence of the trimming upon other circuits.

[0216] In the example, when Vto1 is in the vicinity of Vr1, and thenwhen it repeatedly increases and decreases with respect to Vr1, theoutput signal (code control signal) SEL of the code flattening circuit16 is fixed after detection of the first down edge of Vto1. In such amanner, the output signal SEL of the code flattening circuit 16 is fixedat an optical value at a high speed.

[0217] In the example, when Vto1 (=“3”)<Vr1, the output signal (codecontrol signal) SEL of the code flattening circuit 16 is fixed. However,as shown in the timing chart of FIG. 25, the output signal (code controlsignal) SEL of the code flattening circuit 16 may be fixed when Vto1(=“4”)>Vr1.

[0218] Next, the case where Vto1 periodically increases and decreases bya two-bit length in the vicinity of Vr1 will be explained with referenceto the timing chart of FIG. 26.

[0219] In the initial state, as stated above, Vto1 gradually increasesin synchronism with the clock signal CLK. Under such a condition, sinceVto1 continuously increases, the down detection signal generatingcircuit 18 maintains “L” as the value of, e.g., the down detectionsignal DOWN. At this time, the register 17 does not latch the codecontrol signal, and the multiplexor (MUX) 19 selects and outputs thecode control signal from the code control circuit 13.

[0220] Furthermore, since the value of the code control signal is notthe maximum value, the bit variation monitoring section 20 controls themultiplexor 21 such that the multiplexor 21 selects and outputs theoutput signal of the multiplexor 19.

[0221] When Vto1 is in the vicinity of Vr1, it repeatedly increases anddecreases with respect to Vr1. For example, in the example of FIG. 26,Vto1 varies between “2” and “4”, i.e., it varies by a two-bit lengthwith respect to Vr1.

[0222] The down detection signal generating circuit 18 in the codeflattening circuit 16 makes the down detection signal DOWN “H”, whendetecting that the up/down signal UP/DOWN becomes “L” (DOWN), and thenVto1 decreases.

[0223] As stated above, the down detection signal generating circuit 18may be formed to output the down signal (pulse signal) DOWN whendetecting a down edge (variation from “4” to “3” and that from “3” to“2”) of Vto1.

[0224] The register 17 latches “3” as the code control signal, whenreceiving the first down detection signal DOWN, and thereafter, does notaccept the input signal. At the same time, the multiplexor 19 selectsand outputs the output signal of the register 17, and thereafter alwaysselects and outputs the output signal of the register 17.

[0225] In such a manner, when Vto1 is in the vicinity of Vr1, the codeflattening circuit 16 fixes the code control signal (code value) at avalue at which Vto1 is closest to Vr1, i.e., “3” in this example. Thus,in precision trimming of the example, the resistance value (code value)of the resistor Rto use for use in actual trimming of an outputimpedance can be fixed at an optimal value at a high speed, and thus, itis not necessary to consider the influence of the internal circuits uponexternal circuits.

[0226] In the example also, the output signal (code control signal) SELof the code flattening circuit 16 is fixed when the first down edge ofVto1 is detected. In such a manner, the output signal SEL of the codeflattening circuit 16 is fixed at an optimal value at a high speed.

[0227] Further, in the example, Vto1 varies by a two-bit length withrespect to Vr1. Thus, the code flattening circuit 16 fixes the outputsignal (code control signal) SEL when Vto1 (=“3”)=Vr1. In such a manner,in the example, trimming of the output impedance can be carried out at ahigh precision.

[0228]FIG. 27 shows a timing chart of Vto1 which varies with respect tothe maximum value “7”. At this time, the bit variation monitoringcircuit 20 forcibly outputs a predetermined value, which is “6” in thisexample, as the output signal SEL of the code flattening circuit 16,regardless of the code control signal from the code control circuit 13.

(3) EXAMPLE 2 of the Circuit

[0229]FIG. 28 shows example 2 of the impedance trimming circuitaccording to the ninth embodiment of the present invention.

[0230] The impedance trimming circuit provided as example 2 is an inputimpedance trimming circuit. This circuit does not need the driver dummyresistor or the driver, and merely performs trimming of the resistor,and adjusts the input impedance by using the obtained code, unlike theabove output impedance trimming circuit.

[0231] Except the above points, an input impedance trimming circuit 14does not greatly differ from the output impedance trimming section 12shown in FIG. 22. Further, a code flattening circuit 16′ of a codeflattening section 15′ is the same as the code flattening circuit 16 ofthe code flattening section 15 in FIG. 22.

[0232] The operation of the above input impedance trimming circuit isthe same as that of the impedance trimming circuit according to thefirst embodiment, and its explanation will be omitted.

(4) EXAMPLE 3 of the Circuit

[0233]FIG. 29 shows example 3 of the impedance trimming circuitaccording to the ninth embodiment of the present invention.

[0234] The impedance trimming circuit provided as example 3 is aninput/output impedance trimming circuit. This circuit includes an outputimpedance trimming section 12 and an input impedance trimming section14. In this case, a common bias section 11 is shared with the inputimpedance trimming section 12 and the output impedance trimming section14.

[0235] The output impedance trimming section 12 and the code flatteningsection 15 are the same as the output impedance trimming section 12 andcode flattering section 15 shown in FIG. 22. The input impedancetrimming section 14 and the code flattening section 15′ are the same asthe input impedance trimming section 14 and code flattening section 15′shown in FIG. 28.

[0236] The operation of the input/output impedance trimming circuit isthe same as that of the impedance trimming circuit according to thefirst embodiment, and its explanation will be omitted.

[0237] 11. Conclusion

[0238] As described in the first to eighth embodiments, the followingeffects are produced by the impedance trimming circuit according to theexample of the present invention:

[0239] The circuit can be manufactured using a normal CMOS LSImanufacturing process.

[0240] Only one external resistor is required. This is advantageous interms of costs.

[0241] The impedance can be kept constant even with a change in thevalue for the external accurate resistance.

[0242] The impedance can be kept constant even with a change in thelayout of the LSI or in parasitic resistance.

[0243] The number of adjustment codes can be easily increased to easilyaccomplish accurate adjustments.

[0244] The adjustment of the output impedance is also executed on thedriver and is thus very accurate.

[0245] The yield can be easily increased in spite of a wider range ofvariation.

[0246] The circuit can be divided into a number of elements.Accordingly, the elements can be easily shared, and the area of thecircuit can be reduced.

[0247] The resistance values of the resistor elements used in the LSIcan be dynamically determined.

[0248] The resistance values of the resistor elements in the LSI can bedetermined at a high precision, since resistor elements having precisionresistance values are provided outside the LSI.

[0249] The value (code value) of a code control signal for use inimpedance trimming is immediately fixed to an optimal value on the basisof the first down detection signal DOWN. In such a manner, the optimalresistance values of the resistor elements for use in impedance trimmingcan be determined at a high speed. In addition, thereafter, thedetermined resistance values are fixed, and thus, the influence of theinternal circuits upon external circuits can be reduced.

[0250] Especially, when Vto1 varies by a two-bit width with respect toVo1, impedance trimming can be carried out by using a code value(resistance value) at which Vto1 is equal to Vr1. Accordingly, trimmingof high accuracy can be executed.

[0251]FIGS. 30 and 31 show the essential elements of the presentinvention which are used to accomplish these effects. The concept of thepresent invention is that for the resistance values of the resistanceelements, the value Rtrim is set so as to establish a relationshipclosest to Rext:R1=Rtrim:Rt.

[0252] Further, it should be appreciated that within the scope of thisconcept, the following variations are possible.

[0253] The P channel MOS transistor (current driver) is connected to thepower terminal VDD in order to increase an output current from a poweramplifier.

[0254] Likewise, a source follower of the N channel MOS transistor isconnected to the power terminal VDD.

[0255] The resistor R1 is formed inside the LSI so that the resistancevalue of the resistor R1 can be varied in accordance with the resistancevalue of the external resistor Rext.

[0256] The code control circuit is composed of a latch and a coderinstead of the multistage shift register.

[0257] The number of states of a code signal is increased or reduced onthe basis of the relationship between the adjustable variation range andadjustment accuracy.

[0258] Unit resistors of the same shape are arranged close to each otherwithin the LSI in order to improve the relative accuracy for theresistors R1 and Rt.

[0259] The relationship between the reference voltage Vref and the powervoltage VDD is kept constant, and the relationship between the powervoltage VDD and ground voltage VGNBD of the whole circuit is reversed.

[0260] The value for the resistor Rt is adjusted rather than adjustingthe value for the resistor R1 in accordance with the value for theexternal resistor Rext and the parasitic resistance.

[0261] A fixed ratio is maintained between the resistor Rtrim for afeedback system and an actual target impedance trimming resistor (anoutput driver section and an input resistance section).

[0262] In the case where the code control circuit outputs codes thevalues of which decrease by degrees, the down detection signalgenerating circuit in the code flattening circuit is replaced by the upsignal generating circuit.

[0263] The impedance trimming circuit according to the ninth embodimentof the present invention can be applied to various kinds ofsemiconductor integrated circuits which are required to executeimpedance matching with respect to the output impedance, inputimpedance, terminal resistor, or the like.

[0264] As described above, according to the impedance trimming circuitaccording to the example of the present invention, an accurate trimmingoperation can be performed by eliminating the adverse effects ofvariations associated with the LSI manufacturing process. Further, thecircuit can be constructed using a reduced number of external parts,thus reducing manufacturing costs.

[0265] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. An impedance trimming circuit comprising: acommon bias section composed of a first series circuit having a firstinternal resistor and an external resistor connected in series via afirst node and a first operational amplifier having a first inputterminal connected to an internal reference voltage, a second inputterminal connected to the first node, and an output terminal connectedto the first series circuit; and an impedance trimming section composedof a second series circuit having a second internal resistor and animpedance dummy resistor connected in series via a second node, acomparator having a first input terminal connected to the first node anda second input terminal connected to the second node, a code controlcircuit which uses a clock signal to latch an output signal from thecomparator to generate a plurality of switching codes, and a switchingcircuit which uses the plurality of switching codes to switch aresistance value of the impedance dummy resistor, wherein the firstoperational amplifier is also connected to the second series circuit,and an output signal from the code control circuit is inputted to atarget impedance trimming resistor.
 2. The impedance trimming circuitaccording to claim 1, which further comprises a code flattening sectionconfigured to latch one of the plurality of switching codes output fromthe code control circuit, the code flattening circuit fixes a resistancevalue of the target impedance trimming resistor based on said one of theplurality of switching codes.
 3. The impedance trimming circuitaccording to claim 2, wherein when said one of the plurality ofswitching codes output from the code control circuit repeatedlyperiodically varies, said one of the plurality of switching codes islatched by the code flattening section.
 4. The impedance trimmingcircuit according to claim 3, wherein values of the plurality ofswitching codes output from the code control circuit increase by degreesin accordance with an output signal of the comparator, and when thevalue of one of the plurality of switching codes decreases at first, thecode flattening circuit latches one of the plurality of switching codes.5. The impedance trimming circuit according to claim 3, wherein each ofthe plurality of switching codes is expressed by n bits (n=more than 1),and when said one of the plurality of switching codes output from thecode control circuit repeatedly periodically varies between two bits,the code flattening circuit latches one of the two bits.
 6. Theimpedance trimming circuit according to claim 3, wherein each of theplurality of switching codes is expressed by n bits (n=more than 1), andwhen said one of the plurality of switching codes output from the codecontrol circuit repeatedly periodically varies between three bits, thecode flattening circuit latches an intermediate one of the three bits.7. The impedance timing circuit according to claims 1, wherein one ormore pairs of the common bias section and the impedance trimming sectionare present.
 8. The impedance timing circuit according to claims 1,wherein the impedance dummy resistor includes an output buffer.
 9. Theimpedance timing circuit according to claims 1, wherein the impedancedummy resistor includes input impedance, terminal resistance, andpull-up resistance or pull-down resistance.
 10. The impedance timingcircuit according to claims 1, wherein the plurality of switching codesfrom the switching circuit and a resistance value of the impedance dummyresistor exhibit a reciprocal relationship, a polygonal-linerelationship, or an S-shaped relationship.
 11. The impedance timingcircuit according to claims 1, wherein resistance values for the firstand second internal resistors contain parasitic resistance parasitic ona package, a lead, or a frame, and are adjusted to shift an adjustmentrange of the resistance value of the impedance dummy resistor.
 12. Theimpedance timing circuit according to claims 1, wherein the externalresistor is an external accurate resistor, and the resistance values forthe first and second internal resistors can be switched on the basis ofa value for the external resistor.
 13. The impedance timing circuitaccording to claims 1, wherein the resistance values for the first andsecond internal resistors are switched on the basis of the parasiticresistance parasitic on the package, lead, and frame, as well as thevalue for the external resistor.
 14. The impedance timing circuitaccording to claims 1, wherein the first internal resistor is composedof a first and second resistance elements, the first resistor generatesa voltage equal to a difference between a value for the internalreference value during design and a value for the internal referencevalue during operation, and reference values of the first and secondresistance elements are adjusted in accordance with the value for theinternal reference value so as tb meet the following relationship:Rext:R 1under+R 1upper=Rtrip:Rt (where Rext denotes the resistance valueof the external resistor, R1under denotes the resistance value of thefirst resistance element, R1upper denotes the resistance value of thesecond resistance element, Rtrim denotes the resistance value of theimpedance dummy resistor, and Rt denotes a resistance value of thesecond internal resistor).
 15. The impedance timing circuit according toclaims 1, wherein the external resistor is replaced with an internalresistor which operates more accurately than the first and secondinternal resistors and impedance dummy resistor.
 16. The impedancetiming circuit according to claims 1, wherein the impedance trimmingsection has a second operational amplifier, a first input terminal ofthe second operational amplifier is connected to the first seriescircuit, and a second input terminal and an output terminal of thesecond operational amplifier are connected to the second series circuit.17. The impedance trimming circuit according to claims 1, wherein theresistance value of the impedance dummy resistor maintains arelationship with the resistance value of the target impedance trimmingresistor such that the resistance value of the impedance dummy resistoris an integer number of times greater than the resistance value of thetarget impedance trimming resistor.
 18. The impedance trimming circuitaccording to claims 1, wherein the impedance trimming section is one ofan output impedance trimming section and an input impedance trimmingsection, the output impedance trimming section being configured to triman output impedance, the input impedance trimming section beingconfigured to trim an input impedance.
 19. An impedance trimming circuitcomprising: a common bias section comprising a first series circuit anda first operational amplifier, the first series circuit including afirst internal resistor and an external resistor are connected in seriesvia a first node, the first operational amplifier including a firstinput terminal to which an internal reference voltage is to be applied,a second input terminal connected to the first node, and an outputterminal connected to the first series circuit; an output impedancetrimming section comprising a second series circuit, a first comparatorand a first code control circuit, the second series circuit including asecond internal resistor and an output impedance dummy resistor whichare connected in series via a second node, the first comparatorincluding a first input terminal connected to the first node, and asecond input terminal connected to the second node, the first codecontrol circuit latching an output signal of the first comparator as aclock signal, and outputting one of a plurality of first switchingcodes; and an input impedance trimming section comprising a third seriescircuit, a second comparator and a second code control circuit, thethird series circuit including a third internal resistor and an inputimpedance dummy resistor which are connected in series via a third node;the second comparator including a first input terminal connected to thefirst node and a second input terminal connected to the third node, thesecond code control circuit latching an output signal of the secondcomparator as the clock signal, and outputting one of a plurality ofsecond switching codes, wherein: the output terminal of the firstoperational amplifier is connected to the second and third seriescircuits; a resistance value of the output impedance dummy resistor anda resistance value of a first target impedance trimming resistor arechanged by using one of the plurality of first switching codes, theresistance value of the first target impedance trimming resistor beingto be subjected to actual output impedance trimming; and a resistancevalue of the input impedance dummy register and a resistance value of asecond target impedance trimming resistor are changed by using one ofthe plurality of second switching codes, the resistance value of thesecond target impedance trimming resistor being to be subjected toactual input impedance trimming.